1. Technical Field
The present invention relates to the field of customized or application specific integrated circuits. More specifically, the present invention relates to an architecture for providing a customized application specific device having high functional density with high operational speed.
2. Description of the Related Art
There are many conflicting demands on manufacturers of application specific integrated circuits. Customers demand more complexity, but also demand faster development time. In integrated circuit design, the maximum layout density (and thus highest complexity per integrated circuit) is provided by wholly custom layouts. However, custom generation of integrated circuits is very time consuming. It is not possible to meet the customer""s need for quick turn-around with custom layouts. To meet this need while providing good functional density, the use of arrays of standard cells has emerged as a useful architecture.
Standard cell arrays are generally arranged in rows having a fixed width. The cells may have varying length to provide the necessary cell functionality. For example, the simplest cells are inverters. In complementary metal oxide semiconductor (CMOS) designs, an inverter will have one N-channel and one P-channel transistor. In between the rows are routing areas for interconnecting the cells. Power leads may also run through the routing areas or may have designated areas overlying the cell areas. Standard cell arrays have been combined with powerful computerized design tools to provide high functional density with fast order turn-around time. An example of this type of device is the GS30 series provided by Texas Instruments.
However, the standard cell system provides inherent design compromises. To provide high density, an array may be laid out using the minimum row width. For example, a minimum width may be six squares. A square is normalized unit equal to the minimum feature size that can be formed on the integrated circuit. Six square rows provide a very dense array. However, after applying half of the row to P-type transistors and the other half to N-type, the maximum transistor width is about two squares (after including isolation structures between devices). A transistor this small does not provide adequate drive capacity to provide high-speed operation. On the other hand, providing wide rows for high drive transistors reduces the density of the array. The present invention solves this trade-off by providing an architecture that allows for high density and high drive transistors.
It is an object of the present invention to provide an array of customizable functional cells having high density and high drive capacity.
It is a further object of the present invention to provide an architecture that maximizes the width of P-channel transistors in an array of standard cells to compensate for the lower speed operation of P-type devices.
These and other objects are provided by one embodiment of the present invention that includes an integrated circuit having a plurality of first circuit elements, the first circuit elements having a first width. These circuit elements are arranged in a plurality of rows in a semiconductor substrate. The integrated circuit also includes a plurality of second circuit elements having a width of twice the width of the first circuit elements. The second circuit elements are placed in the plurality of rows and occupy the width of two of the first circuit elements.
An additional embodiment of the present invention includes an integrated circuit comprising a plurality of first circuit elements having a first width. The first circuit elements are arranged in a plurality of rows having a plurality of rows in a semiconductor substrate. The rows are divided into a first area of a first conductivity type and a second area of a second conductivity type. The first and second areas alternate in at least two adjacent rows such that the first areas of the at least two adjacent rows are positioned adjacent to each other. The integrated circuit includes a plurality of second circuit elements having a width of twice the first circuit elements. The second circuit elements positioned in the plurality of rows and occupying the width of two of the first circuit elements. At least one of the second circuit elements spans two adjacent rows.